204ghz功率放大器，Psat为6.9dBm，增益为8.8dB，采用65nm CMOS技术

2021 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS) Pub Date : 2021-11-01 DOI:10.1109/comcas52219.2021.9629088

Kobi Ben Atar, E. Socher

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引用次数: 0

摘要

本文设计了一种采用台积电65nm CMOS工艺制作的204GHz功率放大器。该功率放大器采用4条8级并联链和新型输入输出串联组合变压器。输入端4:1分频变压器采用交错反相驱动，插入损耗小于2dB。修改了有源级布局，使最大振荡频率(fmax)提高了50GHz以上。该功率放大器在204GHz时的峰值输出功率为6.9dBm，峰值功率增益为8.8dB, PAE为1%。活性区占模具面积0.17mm2。

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A 204 GHz Power Amplifier with 6.9dBm Psat and 8.8dB Gain in 65nm CMOS Technology

This paper presents the design of a 204GHz power amplifier fabricated in TSMC 65nm CMOS process. The power amplifier employs 4 parallel chains of 8 gain stages with novel input and output series combining transformers. The 4:1 divider transformer at the input is driven in staggered anti-phase, which results in less than 2dB of insertion loss. The active stage layout has been modified to push the maximum oscillation frequency (fmax) by more than 50GHz. The power amplifier produces peak output power of 6.9dBm with 8.8dB of peak power gain at 204GHz, with a PAE of 1%. The active region occupies 0.17mm2 of die area.

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2021 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)

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