芯片多处理器中对交换方法的有效决策单元

J. Weston, Masashi Imai, Tomohide Nagai, T. Nanya
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引用次数: 5

摘要

论文中提出的研究详细介绍了一种被称为“配对和交换”的方法的许多进一步的新发展。Pair和Swap是一种处理器级容错技术,可以在多核芯片中实现优雅的降级。新的发展是基于在系统中引入一个基于硬件的决策单元。决策单元是一种可靠的解决方案,能够在当前核对的基础上可靠地比较一对核的比较结果。决策单元被确定为比核心更可靠、更高效,因为它用于执行比较的体系结构简单性,用于更新每个核心的配置表。本文将详细介绍配对和交换方法中的完整决策单元实现,并展示其检测瞬时和永久故障并优雅地降级的能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors
The research presented in this paper details a number of further novel developments to a methodology known as “Pair and Swap”. Pair and Swap is a processor-level fault tolerance technique that enables graceful degradation in multi-core chips. The new developments are based around the introduction of a, hardware-based, decision unit into the system. The decision unit is a dependable solution to the problem of being able to reliably compare the comparison results of a pair of cores based on the current core pairings. The decision unit is determined to be more reliable, and efficient, than the cores due to the architectural simplicity it uses to perform the comparison, which is used to update eachcore’s configuration table. This paper will detail the complete decision unit implementation within the pair and swap methodology and show its ability to detect and gracefully degrade from both transient and permanent faults.
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