A Novel Machine Learning Attack Resistant APUF with Dual-Edge Acquisition

This paper presents a novel arbiter Physical Unclonable Function (APUF) to overcome the shortcomings of traditional arbiter PUF, such as high hardware cost, low utilization of entropy source and weak anti-attack ability. By shorting the CMOS gate-source, a novel dual-edge acquisition switching component with a full-custom area of 4.292 µm2 is designed to reduce the PUF area and to enhance the deviation-delay time as well as the resistance to machine learning attack. The proposed PUF was full-custom designed in TSMC 65nm CMOS process. Post-layout simulations results show that the proposed PUF has excellent properties of uniqueness, independence and randomness. Specifically, the inter-Puf Hamming Distance at the rising edge, falling edge and between the two edges are 49.863 %, 49.793%, and 50.166% respectively. The PUF output probability of producing “1” at the rising edge (falling edge) is 50.15% (50.03 %). In addition, the attack prediction under 5K training sets at the rising edge (falling edge) is only 50.62% (50.53%) indicating an good resistance to machine learning attack.