Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution

Power dissipated in clock distribution is a major source of total system power dissipation. Instead of increasing wire widths or lengths to reduce skew which results in increased power dissipation, we use a balanced buffer insertion scheme to partition a large clock tree into a number of small subtrees. Because asymmetric loads and wire width variations in small subtrees induce very small skew, minimal wire widths are used. This results in minimal wiring capacitance and dynamic power dissipation. Then the buffer sizing problem is formulated as a constrained optimization problem: minimize power subject to tolerable skew constraints. To minimize skew caused by device parameter variations from die to die, PMOS and NMOS devices in buffers are separately sized. Substantial power reduction is achieved while skews are kept at satisfiable values under all process conditions.