{"title":"NURBS曲线到Be/spl锐角/齐尔曲线转换的并行结构","authors":"P. N. Mallón, M. Bóo, J. Bruguera","doi":"10.1109/EURMIC.2000.874649","DOIUrl":null,"url":null,"abstract":"NURBS are one of the most common methods of representing curves and surfaces in the geometric modeling and computer graphics fields, whilst numerous computer graphics algorithms are based on the utilization of a simpler representation of the same curves and surfaces: Be/spl acute/zier representations. In this paper, we present a parallel architecture to perform the decomposition of a NURBS curve into its constituent Be/spl acute/zier polynomial pieces. This architecture presents a regular and easily scalable structure, suitable for VLSI implementation, which can be efficiently exploited for the decomposition process. The performance of the proposed architecture is improved by the use of carry-save arithmetic, which permits the reduction of the system cycle time.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Parallel architecture for conversion of NURBS curves to Be/spl acute/zier curves\",\"authors\":\"P. N. Mallón, M. Bóo, J. Bruguera\",\"doi\":\"10.1109/EURMIC.2000.874649\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NURBS are one of the most common methods of representing curves and surfaces in the geometric modeling and computer graphics fields, whilst numerous computer graphics algorithms are based on the utilization of a simpler representation of the same curves and surfaces: Be/spl acute/zier representations. In this paper, we present a parallel architecture to perform the decomposition of a NURBS curve into its constituent Be/spl acute/zier polynomial pieces. This architecture presents a regular and easily scalable structure, suitable for VLSI implementation, which can be efficiently exploited for the decomposition process. The performance of the proposed architecture is improved by the use of carry-save arithmetic, which permits the reduction of the system cycle time.\",\"PeriodicalId\":138250,\"journal\":{\"name\":\"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURMIC.2000.874649\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURMIC.2000.874649","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parallel architecture for conversion of NURBS curves to Be/spl acute/zier curves
NURBS are one of the most common methods of representing curves and surfaces in the geometric modeling and computer graphics fields, whilst numerous computer graphics algorithms are based on the utilization of a simpler representation of the same curves and surfaces: Be/spl acute/zier representations. In this paper, we present a parallel architecture to perform the decomposition of a NURBS curve into its constituent Be/spl acute/zier polynomial pieces. This architecture presents a regular and easily scalable structure, suitable for VLSI implementation, which can be efficiently exploited for the decomposition process. The performance of the proposed architecture is improved by the use of carry-save arithmetic, which permits the reduction of the system cycle time.