接口规范和VHDL过程的综合

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410630

P. Gutberlet, W. Rosenstiel

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引用次数: 10

摘要

提出了一种将算法规范与协议层规范分离的方法，允许分层设计。定义了该规范的VHDL子集和方法。作者展示了将不同级别合并到一个同步数据路径中的目标体系结构。他们给出了处理规范中接口部分的算法。最后，给出了一些结果。

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Interface specification and synthesis for VHDL processes

A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given.<>

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来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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