锁相环低功率鉴相器的设计与实现

2019 3rd International Conference on Computing Methodologies and Communication (ICCMC) Pub Date : 2019-03-27 DOI:10.1109/ICCMC.2019.8819745

Kruti P. Thakore, Kehul A. Shah, N. M. Devashrey

{"title":"锁相环低功率鉴相器的设计与实现","authors":"Kruti P. Thakore, Kehul A. Shah, N. M. Devashrey","doi":"10.1109/ICCMC.2019.8819745","DOIUrl":null,"url":null,"abstract":"This paper presents a low power phase frequency detector for Phase lock loop. A presented Low power Phase Frequency Detector is implemented in Cadence virtuoso environment and using GPDK090 Library of 90nm CMOS Technology. The presented Phase Frequency Detector design has total 18 transistors, the total power consumption of the PFD is 10.85 uW@ .1GHz and almost zero dead zone. The occupied area of the presented PFD is 152.55um2 with 1V of supply voltage.","PeriodicalId":232624,"journal":{"name":"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design And Implementation of Low Power Phase Frequency Detector For Phase Lock Loop\",\"authors\":\"Kruti P. Thakore, Kehul A. Shah, N. M. Devashrey\",\"doi\":\"10.1109/ICCMC.2019.8819745\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power phase frequency detector for Phase lock loop. A presented Low power Phase Frequency Detector is implemented in Cadence virtuoso environment and using GPDK090 Library of 90nm CMOS Technology. The presented Phase Frequency Detector design has total 18 transistors, the total power consumption of the PFD is 10.85 uW@ .1GHz and almost zero dead zone. The occupied area of the presented PFD is 152.55um2 with 1V of supply voltage.\",\"PeriodicalId\":232624,\"journal\":{\"name\":\"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)\",\"volume\":\"103 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCMC.2019.8819745\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCMC.2019.8819745","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了一种用于锁相环的低功率相频检测器。采用90nm CMOS技术的GPDK090库，在Cadence virtuoso环境下实现了一种低功耗相位频率检测器。所提出的相位频率检测器设计共有18个晶体管，PFD的总功耗为10.85 uW@ .1 ghz，几乎为零死区。当电源电压为1V时，所述PFD的占地面积为152.55um2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design And Implementation of Low Power Phase Frequency Detector For Phase Lock Loop

This paper presents a low power phase frequency detector for Phase lock loop. A presented Low power Phase Frequency Detector is implemented in Cadence virtuoso environment and using GPDK090 Library of 90nm CMOS Technology. The presented Phase Frequency Detector design has total 18 transistors, the total power consumption of the PFD is 10.85 uW@ .1GHz and almost zero dead zone. The occupied area of the presented PFD is 152.55um2 with 1V of supply voltage.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)

自引率

0.00%

发文量