高斯脉冲信号时序点的数字提取方法

Liu Yong, Xu Jianwu, Wen Tianzhu, Zhang Xicai
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引用次数: 0

摘要

本文实现了一种基于FPGA的高斯插值时间点提取算法。针对有效位小于7位时不能满足定时点误差小于6ns的问题,设计了一种基于FPGA的精确提取高斯脉冲定时点的改进算法。分析了定时误差的来源,比较了采样次数为7、峰值为满量程时直接提取算法、高斯插值算法和改进高斯插值算法的最大误差。结果表明,改进的高斯插值定时算法可以有效地提高定时精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Digital Extraction Method of Gaussian Pulse Signal Timing Point
In this paper, a Gaussian interpolation timing point extraction algorithm based on FPGA is implemented. According to the problem that the timing point error is less than 6ns cannot be satisfied when the effective digit is less than 7 bits, an improved algorithm for accurately extracting Gaussian pulse timing point based on FPGA is designed. Analyzed the source of timing error, the comparison of maximum error between the direct extraction algorithm, Gaussian interpolation algorithm and the improved Gaussian interpolation algorithm is presented when the sampling number is 7 and the peak is full scale. It is concluded that the improved Gaussian interpolation timing algorithm can effectively improve the timing accuracy.
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