设计一个高品质音频专用DSP核心

S. H. Yoon, M. Sunwoo, J. Moon
{"title":"设计一个高品质音频专用DSP核心","authors":"S. H. Yoon, M. Sunwoo, J. Moon","doi":"10.1109/SIPS.2005.1579921","DOIUrl":null,"url":null,"abstract":"This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"388 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design of a high-quality audio-specific DSP core\",\"authors\":\"S. H. Yoon, M. Sunwoo, J. Moon\",\"doi\":\"10.1109/SIPS.2005.1579921\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.\",\"PeriodicalId\":436123,\"journal\":{\"name\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"volume\":\"388 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2005.1579921\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

本文提出了一种专用的DSP架构及其指令,能够有效地支持MPEG-2/4 AAC高质量音频算法。该体系结构针对IMDCT(逆修正离散余弦变换)、霍夫曼解码等进行了专门设计和优化。与TMS320C62x和ASDSP21060相比,IMDCT计算性能有显著提高。此外,专用的霍夫曼加速器仅在2个周期内执行解码过程。该DSP采用三星SEC 0.18 /spl mu/m标准单元库进行合成。所提出的DSP核心由120,283个门组成,运行频率为200mhz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of a high-quality audio-specific DSP core
This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信