{"title":"设计一个高品质音频专用DSP核心","authors":"S. H. Yoon, M. Sunwoo, J. Moon","doi":"10.1109/SIPS.2005.1579921","DOIUrl":null,"url":null,"abstract":"This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"388 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design of a high-quality audio-specific DSP core\",\"authors\":\"S. H. Yoon, M. Sunwoo, J. Moon\",\"doi\":\"10.1109/SIPS.2005.1579921\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.\",\"PeriodicalId\":436123,\"journal\":{\"name\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"volume\":\"388 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2005.1579921\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.