Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells
{"title":"用于低功耗高分辨率adc的16位50kHz 177dB-FOMS无校准无启动SC δ - sigma调制器IP块","authors":"Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells","doi":"10.1109/DCIS51330.2020.9268617","DOIUrl":null,"url":null,"abstract":"This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs\",\"authors\":\"Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells\",\"doi\":\"10.1109/DCIS51330.2020.9268617\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.\",\"PeriodicalId\":186963,\"journal\":{\"name\":\"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCIS51330.2020.9268617\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS51330.2020.9268617","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文介绍了一种用于低功耗高分辨率adc的开关电容Delta-Sigma调制器(ΔΣM) IP块。ΔΣM IP提案不需要任何电路校准,也不需要内部电源启动。一个完整的设计方法,从架构到电路水平与整体功耗的具体优化包括在内。所提出的ΔΣM IP块具有对工艺和温度变化的显著鲁棒性。为了说明问题,本文给出了两个采用1.8 v 180 nm和1.2 v 65 nm混合信号CMOS技术的16位50 khz IP映射示例,其布局后仿真结果显示FOMS值约为177 dB。
A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs
This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.