{"title":"用于中功率射频应用的1.9 GHz低压CMOS功率放大器","authors":"A. Giry, J.-M. Fourniert, M. Pons","doi":"10.1109/RFIC.2000.854430","DOIUrl":null,"url":null,"abstract":"This paper describes the design methodology and measured performances of a monolithic two-stage RF power amplifier realized in a 0.35 /spl mu/m CMOS technology. Under 2.5 V supply, good linearity is achieved and an output power of 23.5 dBm with an associated PAE of 35% is obtained at 19 GHz. The obtained performances give an insight into CMOS potentialities for medium power RF amplification.","PeriodicalId":305585,"journal":{"name":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A 1.9 GHz low voltage CMOS power amplifier for medium power RF applications\",\"authors\":\"A. Giry, J.-M. Fourniert, M. Pons\",\"doi\":\"10.1109/RFIC.2000.854430\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design methodology and measured performances of a monolithic two-stage RF power amplifier realized in a 0.35 /spl mu/m CMOS technology. Under 2.5 V supply, good linearity is achieved and an output power of 23.5 dBm with an associated PAE of 35% is obtained at 19 GHz. The obtained performances give an insight into CMOS potentialities for medium power RF amplification.\",\"PeriodicalId\":305585,\"journal\":{\"name\":\"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2000.854430\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2000.854430","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
摘要
本文介绍了一种以0.35 /spl μ l /m CMOS技术实现的单片两级射频功率放大器的设计方法和实测性能。在2.5 V电源下,实现了良好的线性度,在19 GHz下获得了23.5 dBm的输出功率,相关PAE为35%。所获得的性能为CMOS在中功率射频放大方面的潜力提供了深入的见解。
A 1.9 GHz low voltage CMOS power amplifier for medium power RF applications
This paper describes the design methodology and measured performances of a monolithic two-stage RF power amplifier realized in a 0.35 /spl mu/m CMOS technology. Under 2.5 V supply, good linearity is achieved and an output power of 23.5 dBm with an associated PAE of 35% is obtained at 19 GHz. The obtained performances give an insight into CMOS potentialities for medium power RF amplification.