N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, M. Takikawa
{"title":"高漏极电流密度和高栅导通电压增强模式异质结构场效应晶体管的电流路径优化结构","authors":"N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, M. Takikawa","doi":"10.1109/GAAS.1998.722670","DOIUrl":null,"url":null,"abstract":"We developed a new type of enhancement-mode (E-mode) heterostructure field effect transistors (FETs) which provide single-voltage operation of power amplifiers in portable phone handsets. Gate leakage current paths were optimized, and a high gate-turn-on voltage and a high drain current density were obtained at the same time. This allows a 50% increase of the drain current by shortening the gate-to-source length without increasing the gate leakage current. We applied this technique to completely E-mode FETs (Vth>0.3 V). A power added efficiency as high as 70.6% has been achieved for an output power of 33 dBm under a Vds of 3.5 V at 850 MHz.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Current path optimized structure for high drain current density and high gate-turn-on voltage enhancement mode heterostructure field effect transistors\",\"authors\":\"N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, M. Takikawa\",\"doi\":\"10.1109/GAAS.1998.722670\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We developed a new type of enhancement-mode (E-mode) heterostructure field effect transistors (FETs) which provide single-voltage operation of power amplifiers in portable phone handsets. Gate leakage current paths were optimized, and a high gate-turn-on voltage and a high drain current density were obtained at the same time. This allows a 50% increase of the drain current by shortening the gate-to-source length without increasing the gate leakage current. We applied this technique to completely E-mode FETs (Vth>0.3 V). A power added efficiency as high as 70.6% has been achieved for an output power of 33 dBm under a Vds of 3.5 V at 850 MHz.\",\"PeriodicalId\":288170,\"journal\":{\"name\":\"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1998.722670\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1998.722670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Current path optimized structure for high drain current density and high gate-turn-on voltage enhancement mode heterostructure field effect transistors
We developed a new type of enhancement-mode (E-mode) heterostructure field effect transistors (FETs) which provide single-voltage operation of power amplifiers in portable phone handsets. Gate leakage current paths were optimized, and a high gate-turn-on voltage and a high drain current density were obtained at the same time. This allows a 50% increase of the drain current by shortening the gate-to-source length without increasing the gate leakage current. We applied this technique to completely E-mode FETs (Vth>0.3 V). A power added efficiency as high as 70.6% has been achieved for an output power of 33 dBm under a Vds of 3.5 V at 850 MHz.