CMOS缩放到25nm栅极长度

The Fourth International Conference on Advanced Semiconductor Devices and Microsystem Pub Date : 2002-12-16 DOI:10.1109/ASDAM.2002.1088521

S. Kubicek, K. De Meyer

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引用次数: 2

摘要

本文综述了将CMOS技术缩小到25nm栅极长度的一些器件和工艺问题。首先从器件的角度讨论了缩放问题，并确定了与器件相关的主要问题。以下是ITRS路线图的历史趋势和预测概述。对特定器件工艺模块的缩放预测的含义进行了回顾，并提出了最近的实验数据。

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CMOS scaling to 25 nm gate lengths

In this paper some of the device and process issues of scaling CMOS technology down to 25 nm gate lengths are reviewed. First scaling is discussed front a device perspective and the main device related issues are identified. An overview of the historical trends and predictions by the ITRS roadmap follows. Implications of the scaling predictions for the specific device process modules are reviewed and recent experimental data are presented.

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The Fourth International Conference on Advanced Semiconductor Devices and Microsystem

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