{"title":"ZnO tft表面电位的经验模型及模拟分析","authors":"Anirudh Aggarwal, R. Goswami, Kavindra Kandpal","doi":"10.1109/DEVIC.2019.8783775","DOIUrl":null,"url":null,"abstract":"This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Empirical Model of Surface Potential and Simulation Analyses for ZnO TFTs\",\"authors\":\"Anirudh Aggarwal, R. Goswami, Kavindra Kandpal\",\"doi\":\"10.1109/DEVIC.2019.8783775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.\",\"PeriodicalId\":294095,\"journal\":{\"name\":\"2019 Devices for Integrated Circuit (DevIC)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Devices for Integrated Circuit (DevIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DEVIC.2019.8783775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Empirical Model of Surface Potential and Simulation Analyses for ZnO TFTs
This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.
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