高速数字混合锁相环频率合成器

Hun-Hee Lee, Wonhui Park, H. Ryu
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引用次数: 4

摘要

传统锁相环频率合成器由于其固有的闭环结构,开关时间较长。为了克服这一问题,研究了在传统锁相环合成器中加入开环结构的数字混合锁相环(DH-PLL)。它运行速度快,但由于DLT(数字查找表)通常由包含VCO(压控振荡器)传输特性的ROM实现,因此硬件复杂性和功耗是另一个严重的问题。本文提出了一种新的DH-PLL,使用非常简单的DLT替换数字逻辑代替复杂的rom型DLT。同时,一个定时同步电路使得超调量可以忽略不计,并且在超快的开关速度下更短的稳定时间。此外,与传统的DH-PLL相比,硬件复杂度和功耗降低了约28%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High speed digital hybrid PLL frequency synthesizer
The conventional PLL (phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are another serious problems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed. Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL.
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