{"title":"分支绑定算法的异步多处理器设计","authors":"Kam-Hoi Cheng, Q. Wang","doi":"10.1109/FMPC.1990.89440","DOIUrl":null,"url":null,"abstract":"A fast asynchronous multiprocessor system designed to implement branch-and-bound algorithms is described. Cooperating processors are only responsible for performing computation essential to the problem. Dynamic sharing of work and coordinate among processors are provided by several servers, all of which are capable of handling multiple accesses simultaneously. It is shown how to coordinate the use of these designs and prove the correctness of the authors' solution in reactivating idle processors and detecting the termination of the computation. The loss of computation power due to the uneven work-load distribution, coordination, and synchronization of processors has been reduced significantly compared with other hardware designs.<<ETX>>","PeriodicalId":193332,"journal":{"name":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An asynchronous multiprocessor design for branch-and-bound algorithms\",\"authors\":\"Kam-Hoi Cheng, Q. Wang\",\"doi\":\"10.1109/FMPC.1990.89440\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast asynchronous multiprocessor system designed to implement branch-and-bound algorithms is described. Cooperating processors are only responsible for performing computation essential to the problem. Dynamic sharing of work and coordinate among processors are provided by several servers, all of which are capable of handling multiple accesses simultaneously. It is shown how to coordinate the use of these designs and prove the correctness of the authors' solution in reactivating idle processors and detecting the termination of the computation. The loss of computation power due to the uneven work-load distribution, coordination, and synchronization of processors has been reduced significantly compared with other hardware designs.<<ETX>>\",\"PeriodicalId\":193332,\"journal\":{\"name\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FMPC.1990.89440\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1990.89440","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An asynchronous multiprocessor design for branch-and-bound algorithms
A fast asynchronous multiprocessor system designed to implement branch-and-bound algorithms is described. Cooperating processors are only responsible for performing computation essential to the problem. Dynamic sharing of work and coordinate among processors are provided by several servers, all of which are capable of handling multiple accesses simultaneously. It is shown how to coordinate the use of these designs and prove the correctness of the authors' solution in reactivating idle processors and detecting the termination of the computation. The loss of computation power due to the uneven work-load distribution, coordination, and synchronization of processors has been reduced significantly compared with other hardware designs.<>