{"title":"一个10位纳安培级电流转向数模转换器","authors":"Qiang Huang, Jun Feng","doi":"10.1109/ISCIT.2013.6645861","DOIUrl":null,"url":null,"abstract":"A 10-bit Digital-to-Analog Converter (DAC) in Charted 0.35um technology is presented. The design realizes a 10-bit, 25MS/s sampling rate and 10nA of the least significant bit output current DAC in the current steering structure. The whole DAC consists of synchronous unit circuit, decoding circuit, switch array, voltage-current transition circuit, current source array, output current mirror and so on. The area of the chip is 1.15μm×1.28μm. The power supply is 3.3V, the static power consumption is 4.8mW, the integral nonlinearity (INL) is 1LSB, the differential nonlinearity (DNL) is 1LSB. The test shows that the chip has a good performance on linearity when linearly increasing data is input.","PeriodicalId":356009,"journal":{"name":"2013 13th International Symposium on Communications and Information Technologies (ISCIT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 10-bit nanoampere level current-steering Digital to Analog Converter\",\"authors\":\"Qiang Huang, Jun Feng\",\"doi\":\"10.1109/ISCIT.2013.6645861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit Digital-to-Analog Converter (DAC) in Charted 0.35um technology is presented. The design realizes a 10-bit, 25MS/s sampling rate and 10nA of the least significant bit output current DAC in the current steering structure. The whole DAC consists of synchronous unit circuit, decoding circuit, switch array, voltage-current transition circuit, current source array, output current mirror and so on. The area of the chip is 1.15μm×1.28μm. The power supply is 3.3V, the static power consumption is 4.8mW, the integral nonlinearity (INL) is 1LSB, the differential nonlinearity (DNL) is 1LSB. The test shows that the chip has a good performance on linearity when linearly increasing data is input.\",\"PeriodicalId\":356009,\"journal\":{\"name\":\"2013 13th International Symposium on Communications and Information Technologies (ISCIT)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 13th International Symposium on Communications and Information Technologies (ISCIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCIT.2013.6645861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 13th International Symposium on Communications and Information Technologies (ISCIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2013.6645861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10-bit nanoampere level current-steering Digital to Analog Converter
A 10-bit Digital-to-Analog Converter (DAC) in Charted 0.35um technology is presented. The design realizes a 10-bit, 25MS/s sampling rate and 10nA of the least significant bit output current DAC in the current steering structure. The whole DAC consists of synchronous unit circuit, decoding circuit, switch array, voltage-current transition circuit, current source array, output current mirror and so on. The area of the chip is 1.15μm×1.28μm. The power supply is 3.3V, the static power consumption is 4.8mW, the integral nonlinearity (INL) is 1LSB, the differential nonlinearity (DNL) is 1LSB. The test shows that the chip has a good performance on linearity when linearly increasing data is input.
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