Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, J. Zhu
{"title":"基于非线性cnn的28纳米CMOS硬盘读通道误差率降低30%,连续吞吐量200Mbits/s","authors":"Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, J. Zhu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830238","DOIUrl":null,"url":null,"abstract":"In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS\",\"authors\":\"Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, J. Zhu\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830238\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830238\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS
In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.