3D AND:实现高密度和快速读取的3D NOR闪存和存储级存储器的3D可堆叠闪存架构

H. Lue, Guan-Ru Lee, T. Yeh, T. Hsu, C. Lo, Cheng-Lin Sung, Wei-Chen Chen, Chiatze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, C. Chiu, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu
{"title":"3D AND:实现高密度和快速读取的3D NOR闪存和存储级存储器的3D可堆叠闪存架构","authors":"H. Lue, Guan-Ru Lee, T. Yeh, T. Hsu, C. Lo, Cheng-Lin Sung, Wei-Chen Chen, Chiatze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, C. Chiu, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IEDM13553.2020.9372101","DOIUrl":null,"url":null,"abstract":"We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory\",\"authors\":\"H. Lue, Guan-Ru Lee, T. Yeh, T. Hsu, C. Lo, Cheng-Lin Sung, Wei-Chen Chen, Chiatze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, C. Chiu, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu\",\"doi\":\"10.1109/IEDM13553.2020.9372101\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).\",\"PeriodicalId\":415186,\"journal\":{\"name\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM13553.2020.9372101\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9372101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

我们展示了一种用于高密度和快速读取非易失性存储解决方案的3D可堆叠and型闪存架构。该器件基于栅极全能(GAA)通心粉薄体器件,用两条垂直埋置扩散线通过掺杂N+的聚塞将所有存储单元并联连接,实现3D and型阵列。>6uA的高传感电流可实现像NOR Flash一样的快进~100ns,而该结构最终可实现数百层堆叠。使用BE-MANOS电荷捕获装置,在我们的3D架构中演示了>5阶的大晶体管开/关比,>5V Vt存储窗口,100K耐久性,无读干扰特性和小RTN。该架构有望实现高密度3D NOR闪存和未来存储级存储器(SCM)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory
We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信