Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors

Near-threshold voltage (NTV) design has been proposed for low-power VLSI designs across a wide range of applications due to its optimal Energy-Delay Product. Dynamic Voltage and Frequency Scaling (DVFS) design has acquired recent interest to increase energy efficiency during runtime. During periods of low utilization, a chip’s performance and power consumption can be adjusted by slowing down the clock speed and decreasing the supply voltage, thereby bringing its operation to the NTV region. However, high dynamic variations at low voltage operation is the key design challenge and barrier for near-threshold adoption. Hence, it becomes mandatory to consider large timing margins during design to ensure high yield and robust operation. Error resilient circuits help to restore the timing margins, thereby improving performance with low power consumption. This paper presents EDTB (Error Detection with Time-Borrowing), a novel architecture for multi-stage timing error resilience which masks timing errors by borrowing time from successive pipeline stages, without slowing down the clock speed. The proposed error handling scheme doesn’t require error recovery mechanisms like instruction replay or roll-back; hence it doesn’t associate any error recovery penalty. EDTB-based error masking is resilient to glitches and spurious transitions due to its minimal hold time requirement. EDTB architecture shows a significant improvement of up to 34% in transistor count and 50% in clock routing over the previous architecture. The circuit schematic was prototyped in Cadence Virtuoso ADE in a 7-nm FinFET based predictive process design kit; followed by simulation, validation, and further comparisons.