{"title":"用于帧交换网络的通用10gbps组装边缘节点和测试平台","authors":"A. Mutter, M. Köhn, M. Sund","doi":"10.1109/TRIDENTCOM.2009.4976201","DOIUrl":null,"url":null,"abstract":"Packet assembly at the network edge is one solution to reduce the high packet rates in core network switches. For this, specialized edge nodes called Assembly Units are needed that assemble client packets into containers and vice versa. In this paper we present the detailed architecture and implementation of a generic Frame Assembly Unit for the Frame Switching architecture along with the testbed used for validation. Our design supports timer and threshold based assembly including packet fragmentation for fixed and variable size container frames at 10 Gbps per direction. For assembly and packet delineation we use the ITU-T Generic Framing Procedure. We report performance and implementation results for an overall design that operates with a 128 Bit data-path at 100 MHz on Xilinx Virtex4 FPGAs","PeriodicalId":254380,"journal":{"name":"2009 5th International Conference on Testbeds and Research Infrastructures for the Development of Networks & Communities and Workshops","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A generic 10 Gbps assembly edge node and testbed for frame switching networks\",\"authors\":\"A. Mutter, M. Köhn, M. Sund\",\"doi\":\"10.1109/TRIDENTCOM.2009.4976201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Packet assembly at the network edge is one solution to reduce the high packet rates in core network switches. For this, specialized edge nodes called Assembly Units are needed that assemble client packets into containers and vice versa. In this paper we present the detailed architecture and implementation of a generic Frame Assembly Unit for the Frame Switching architecture along with the testbed used for validation. Our design supports timer and threshold based assembly including packet fragmentation for fixed and variable size container frames at 10 Gbps per direction. For assembly and packet delineation we use the ITU-T Generic Framing Procedure. We report performance and implementation results for an overall design that operates with a 128 Bit data-path at 100 MHz on Xilinx Virtex4 FPGAs\",\"PeriodicalId\":254380,\"journal\":{\"name\":\"2009 5th International Conference on Testbeds and Research Infrastructures for the Development of Networks & Communities and Workshops\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 5th International Conference on Testbeds and Research Infrastructures for the Development of Networks & Communities and Workshops\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TRIDENTCOM.2009.4976201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 5th International Conference on Testbeds and Research Infrastructures for the Development of Networks & Communities and Workshops","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TRIDENTCOM.2009.4976201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A generic 10 Gbps assembly edge node and testbed for frame switching networks
Packet assembly at the network edge is one solution to reduce the high packet rates in core network switches. For this, specialized edge nodes called Assembly Units are needed that assemble client packets into containers and vice versa. In this paper we present the detailed architecture and implementation of a generic Frame Assembly Unit for the Frame Switching architecture along with the testbed used for validation. Our design supports timer and threshold based assembly including packet fragmentation for fixed and variable size container frames at 10 Gbps per direction. For assembly and packet delineation we use the ITU-T Generic Framing Procedure. We report performance and implementation results for an overall design that operates with a 128 Bit data-path at 100 MHz on Xilinx Virtex4 FPGAs