Resource-efficient FPGA architecture of Canny edge detector

Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.