{"title":"纳米技术中的超紧凑MOS模型","authors":"Elio Consoli, G. Giustolisi, G. Palumbo","doi":"10.1109/ECCTD.2011.6043403","DOIUrl":null,"url":null,"abstract":"In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An ultra-compact MOS model in nanometer technologies\",\"authors\":\"Elio Consoli, G. Giustolisi, G. Palumbo\",\"doi\":\"10.1109/ECCTD.2011.6043403\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.\",\"PeriodicalId\":126960,\"journal\":{\"name\":\"2011 20th European Conference on Circuit Theory and Design (ECCTD)\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 20th European Conference on Circuit Theory and Design (ECCTD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2011.6043403\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2011.6043403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ultra-compact MOS model in nanometer technologies
In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.