High Performance Implementation of Nested Array Beamformer for Wideband Radar Applications

Beamformer is an important part of the wideband radar systems. An approach to achieve the high sampling rate required in such systems is to use efficient hardware implementations. This paper presents a speed optimized systolic arrays for implementation of the wideband beamformer using nested arrays, 2-D filters, and multirate techniques. The implementation structures of the beamformer basic building blocks are designed based on systematic methodology and implemented using the field programmable gate array (FPGA) platform targeting Basys- 3 development board’s Xilinx Artix-7 (XC7A100T) FPGA chip. A single channel of the beamformer was chosen for the implementation to confirm the correct functionality of the FPGA architecture. The implementation performance is tested in terms of effect of errors due to finite word-length arithmetic.