{"title":"用于SHARC信号处理器的性能评估工具集","authors":"S. Sair, Guiseppe Olivadoti, D. Kaeli, J. Fridman","doi":"10.1109/SIMSYM.2000.844900","DOIUrl":null,"url":null,"abstract":"Performance tuning in the embedded systems domain poses a new set of challenges for software and hardware designers. Techniques proven to work for general purpose architectures cannot always be directly applied to the signal processor environment. Program analysis and simulation tools have been shown to be available in the analysis of general purpose microprocessors. We anticipate that similar tools will be needed to analyze the characteristics of signal processing architectures and applications as well. To meet this need, we have developed DSPTune, a program analysis toolset for the Analog Devices' SHARC DSP. This paper describes our toolset, and provides examples of its use.","PeriodicalId":361153,"journal":{"name":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"DSPTune: a performance evaluation toolset for the SHARC signal processor\",\"authors\":\"S. Sair, Guiseppe Olivadoti, D. Kaeli, J. Fridman\",\"doi\":\"10.1109/SIMSYM.2000.844900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Performance tuning in the embedded systems domain poses a new set of challenges for software and hardware designers. Techniques proven to work for general purpose architectures cannot always be directly applied to the signal processor environment. Program analysis and simulation tools have been shown to be available in the analysis of general purpose microprocessors. We anticipate that similar tools will be needed to analyze the characteristics of signal processing architectures and applications as well. To meet this need, we have developed DSPTune, a program analysis toolset for the Analog Devices' SHARC DSP. This paper describes our toolset, and provides examples of its use.\",\"PeriodicalId\":361153,\"journal\":{\"name\":\"Proceedings 33rd Annual Simulation Symposium (SS 2000)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 33rd Annual Simulation Symposium (SS 2000)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIMSYM.2000.844900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 33rd Annual Simulation Symposium (SS 2000)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIMSYM.2000.844900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
DSPTune: a performance evaluation toolset for the SHARC signal processor
Performance tuning in the embedded systems domain poses a new set of challenges for software and hardware designers. Techniques proven to work for general purpose architectures cannot always be directly applied to the signal processor environment. Program analysis and simulation tools have been shown to be available in the analysis of general purpose microprocessors. We anticipate that similar tools will be needed to analyze the characteristics of signal processing architectures and applications as well. To meet this need, we have developed DSPTune, a program analysis toolset for the Analog Devices' SHARC DSP. This paper describes our toolset, and provides examples of its use.
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