Temperature Characterisation of the DSP Delay Line

Time-to-Digital Converters (TDCs) are important measurement devices for fields such as quantum computing and range-finding. To implement these devices, FPGAs are an attractive option due to their low cost relative to ASICs, reconfigurability, updatability and off-the-shelf availability. However, these devices are often sensitive to changes in temperature due to temperature-dependent changes in electrical characteristics (Process-Voltage-Temperature, PVT variations), and thus must be characterised to avoid erroneous measurements. In our past papers, we demonstrated the implementation of Tapped Delay Line (TDL) TDCs using the DSP blocks available on Xilinx FPGAs. In this paper, we characterise the variability of the TDC core with respect to temperature in terms of Single-Shot Precision (SSP), resolution, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL). Over a temperature range of 68.3° C, we demonstrate an 8.23 ps difference in SSP, a 3.89 ps difference in cubic-mean resolution, a 247 ps difference in INL and a 19.4 ps difference in DNL.