基于FPGA实现的高级加密标准

Sujatha Hiremath, M. Suma
{"title":"基于FPGA实现的高级加密标准","authors":"Sujatha Hiremath, M. Suma","doi":"10.1109/ICCEE.2009.231","DOIUrl":null,"url":null,"abstract":"Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.","PeriodicalId":343870,"journal":{"name":"2009 Second International Conference on Computer and Electrical Engineering","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Advanced Encryption Standard Implemented on FPGA\",\"authors\":\"Sujatha Hiremath, M. Suma\",\"doi\":\"10.1109/ICCEE.2009.231\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.\",\"PeriodicalId\":343870,\"journal\":{\"name\":\"2009 Second International Conference on Computer and Electrical Engineering\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Second International Conference on Computer and Electrical Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCEE.2009.231\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Second International Conference on Computer and Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCEE.2009.231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

摘要

高级加密标准(AES),联邦信息处理标准(FIPS),并归类为计算机安全标准。AES算法是一种分组密码,可以对数字信息进行加密和解密。AES算法可以使用128位、192位和256位的密钥。Rijndael密码已被选为官方高级加密标准(AES),它非常适合硬件。本文讨论了AES 128位分组和128位密钥,并在Spartan 3 FPGA上实现。合成结果使用了2509个切片,712个触发器和4762- 4个输入查找表。设计目标是速度和成本的优化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Advanced Encryption Standard Implemented on FPGA
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.
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