{"title":"概率并行遗传算法的性能评估:FPGA与多核处理器","authors":"Y. Jewajinda","doi":"10.1109/ICSEC.2013.6694797","DOIUrl":null,"url":null,"abstract":"This paper presents a performance evaluation between hardware and software implementation of a probabilistic parallel genetic algorithm. The compact genetic algorithm is extended to support parallel implementation. The parallelized compact genetic algorithm is implemented in FPGA hardware and parallelized software version running on multicore processors for performance evaluation using standard benchmark functions. The experimental results show that the hardware implementation of the parallel compact genetic algorithm delivers speedup of between 100-fold to 500-fold depending on problems size and number of generations.","PeriodicalId":191620,"journal":{"name":"2013 International Computer Science and Engineering Conference (ICSEC)","volume":"8 16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A performance evaluation of a probabilistic parallel genetic algorithm: FPGA vs. multi-core processor\",\"authors\":\"Y. Jewajinda\",\"doi\":\"10.1109/ICSEC.2013.6694797\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a performance evaluation between hardware and software implementation of a probabilistic parallel genetic algorithm. The compact genetic algorithm is extended to support parallel implementation. The parallelized compact genetic algorithm is implemented in FPGA hardware and parallelized software version running on multicore processors for performance evaluation using standard benchmark functions. The experimental results show that the hardware implementation of the parallel compact genetic algorithm delivers speedup of between 100-fold to 500-fold depending on problems size and number of generations.\",\"PeriodicalId\":191620,\"journal\":{\"name\":\"2013 International Computer Science and Engineering Conference (ICSEC)\",\"volume\":\"8 16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 International Computer Science and Engineering Conference (ICSEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSEC.2013.6694797\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Computer Science and Engineering Conference (ICSEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSEC.2013.6694797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A performance evaluation of a probabilistic parallel genetic algorithm: FPGA vs. multi-core processor
This paper presents a performance evaluation between hardware and software implementation of a probabilistic parallel genetic algorithm. The compact genetic algorithm is extended to support parallel implementation. The parallelized compact genetic algorithm is implemented in FPGA hardware and parallelized software version running on multicore processors for performance evaluation using standard benchmark functions. The experimental results show that the hardware implementation of the parallel compact genetic algorithm delivers speedup of between 100-fold to 500-fold depending on problems size and number of generations.