Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim
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引用次数: 9
摘要
开发了一种31 mW, 10位100 MS/s的流水线ADC。所提出的ADC通过采用一种新的opamp共享技术，将MDAC中的求和节点和带PVT状态检测器的电流源切换，实现了低功耗、高抗噪性和小面积。ADC的DNL小于0.48 LSB, INL小于0.95 LSB。此外，在1 MHz输入频率下测量到56.2 dB的SNDR。它已在0.18 um CMOS工艺中实现，占用1.6 x 0.8 mm2的有源面积。
10-bit 100MS/s CMOS pipelined A/D converter with 0.59pJ/conversion-step
A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a 1 MHz input frequency. It has been implemented in a 0.18 um CMOS process and it occupies 1.6 x 0.8 mm2 of active area.
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