打破比较-选择反馈瓶颈的并行维特比译码

IEEE International Conference on Communications, - Spanning the Universe. Pub Date : 1988-06-12 DOI:10.1109/ICC.1988.13656

G. Fettweis, H. Meyr

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引用次数: 35

摘要

提出了一种采用并行硬件实现高数据速率维特比解码器的加比较选择(ACS)单元的解决方案。对于给定硬件的固定处理速度，它允许通过硬件复杂性的线性增加来线性增加吞吐量。因此，任意吞吐率可以通过线性增加更多的并行硬件元素来实现。本文提出了一种Viterbi解码器的并行ACS单元的收缩阵列实现

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Parallel Viterbi decoding by breaking the compare-select feedback bottleneck

A solution is presented for implementing the add-compare-select (ACS) unit of a Viterbi decoder by parallel hardware for high data rates. For a fixed processing speed of the given hardware it allows a linear increase in throughput rate by a linear increase in hardware complexity. Thus arbitrary throughput rates can be achieved by linearly adding more parallel hardware elements. A systolic-array implementation of this parallel ACS unit of a Viterbi decoder is presented.<>

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IEEE International Conference on Communications, - Spanning the Universe.

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