{"title":"低功耗高倍率精密电容倍增器","authors":"Shashwat Singh, Jatin, N. Pandey, R. Pandey","doi":"10.1109/SPIN.2018.8474039","DOIUrl":null,"url":null,"abstract":"Second Generation Current Conveyors (CCIIs) based capacitance multiplier, suitable for resolving a large grounded capacitor is proposed in this paper. The realization is convenient for further integration in ICs. The effects of CCIIs non-idealities are also elaborated. The simulation results of proposed capacitance multiplier is accomplished using SPICE that holds true with the theoretical predictions.","PeriodicalId":184596,"journal":{"name":"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Precision Capacitance Multiplier with Low Power and High Multiplication Factor\",\"authors\":\"Shashwat Singh, Jatin, N. Pandey, R. Pandey\",\"doi\":\"10.1109/SPIN.2018.8474039\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Second Generation Current Conveyors (CCIIs) based capacitance multiplier, suitable for resolving a large grounded capacitor is proposed in this paper. The realization is convenient for further integration in ICs. The effects of CCIIs non-idealities are also elaborated. The simulation results of proposed capacitance multiplier is accomplished using SPICE that holds true with the theoretical predictions.\",\"PeriodicalId\":184596,\"journal\":{\"name\":\"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN.2018.8474039\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN.2018.8474039","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Precision Capacitance Multiplier with Low Power and High Multiplication Factor
Second Generation Current Conveyors (CCIIs) based capacitance multiplier, suitable for resolving a large grounded capacitor is proposed in this paper. The realization is convenient for further integration in ICs. The effects of CCIIs non-idealities are also elaborated. The simulation results of proposed capacitance multiplier is accomplished using SPICE that holds true with the theoretical predictions.