9b 100MS/s 1.46mW SAR ADC, 65nm CMOS

2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI:10.1109/ASSCC.2009.5357199

Yanfei Chen, Sanroku Tsukamoto, T. Kuroda

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引用次数: 46

摘要

在65nm CMOS上实现了一个9b 100MS/s逐次逼近寄存器(SAR) ADC，其有效面积为0.012mm2。基于三电平的电荷重分配技术通过连接差分电容阵列的底板来提高DAC开关能量效率和稳定时间。该ADC的SNDR为53.1dB (8.53 ENOB)， 1.2V电源的功耗为1.46mW, FOM为39fJ/转换步长。

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A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

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2009 IEEE Asian Solid-State Circuits Conference

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