{"title":"基于HLS和PCIe的ARM和FPGA异构加速处理系统","authors":"Zhonghao Zhang, Zhengxiang Li","doi":"10.1109/ICICT52872.2021.00055","DOIUrl":null,"url":null,"abstract":"Nowadays, with the development of highperformance computing, heterogeneous computing system has become a trend. This paper designs an CPU+FPGA heterogeneous accelerated processing system that uses embedded ARM and FPGA to communicate via PCIe bus. The system mainly uses the Jetson TX2 ARM development board, the development board and FPGA board are connected via PCIe, and High-Level Synthesis (HLS) method is used to transplant the implemented algorithms needed in the project to the FPGA. The focus of this article is: how to use XDMA IP core to connect FPGA and ARM processor through PCIe bus, and how to use HLS to generate IP core. The article completed the architecture design, analyzed the working mechanism of the XDMA kernel module in the Linux system, and analyzed the system bandwidth and delay.","PeriodicalId":359456,"journal":{"name":"2021 4th International Conference on Information and Computer Technologies (ICICT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ARM and FPGA Heterogeneous Accelerated Processing System Based on HLS and PCIe\",\"authors\":\"Zhonghao Zhang, Zhengxiang Li\",\"doi\":\"10.1109/ICICT52872.2021.00055\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nowadays, with the development of highperformance computing, heterogeneous computing system has become a trend. This paper designs an CPU+FPGA heterogeneous accelerated processing system that uses embedded ARM and FPGA to communicate via PCIe bus. The system mainly uses the Jetson TX2 ARM development board, the development board and FPGA board are connected via PCIe, and High-Level Synthesis (HLS) method is used to transplant the implemented algorithms needed in the project to the FPGA. The focus of this article is: how to use XDMA IP core to connect FPGA and ARM processor through PCIe bus, and how to use HLS to generate IP core. The article completed the architecture design, analyzed the working mechanism of the XDMA kernel module in the Linux system, and analyzed the system bandwidth and delay.\",\"PeriodicalId\":359456,\"journal\":{\"name\":\"2021 4th International Conference on Information and Computer Technologies (ICICT)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 4th International Conference on Information and Computer Technologies (ICICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICT52872.2021.00055\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 4th International Conference on Information and Computer Technologies (ICICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICT52872.2021.00055","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ARM and FPGA Heterogeneous Accelerated Processing System Based on HLS and PCIe
Nowadays, with the development of highperformance computing, heterogeneous computing system has become a trend. This paper designs an CPU+FPGA heterogeneous accelerated processing system that uses embedded ARM and FPGA to communicate via PCIe bus. The system mainly uses the Jetson TX2 ARM development board, the development board and FPGA board are connected via PCIe, and High-Level Synthesis (HLS) method is used to transplant the implemented algorithms needed in the project to the FPGA. The focus of this article is: how to use XDMA IP core to connect FPGA and ARM processor through PCIe bus, and how to use HLS to generate IP core. The article completed the architecture design, analyzed the working mechanism of the XDMA kernel module in the Linux system, and analyzed the system bandwidth and delay.