Energy Efficient CNTFET based Dual Mode Logic (C-DML) Design

To incorporate the benefits of both Carbon Nano Tube Field Effect Transistor (CNTFET) transistor technology and footed Dual Mode Logic (DML) style, this contribution introduces an energy efficient CNTFET based Dual Mode Logic style and is referred to as C-DML. Owing to continuous transistor scaling, MOSFET based DML design suffers large parametric variations, short channel effects, high heat dissipation and decreased gate control. To resolve these issues, the C-DML design is proposed and simulated for 2-input NAND, NOR and 2:1 multiplexer circuit using HSPICE tool with 32nm CNTFET Stanford model at 0.9V and 5fF load capacitance in static and dynamic mode for both footed type A and type B configuration. Power, delay, and PDP are used to compare the existing CMOS and proposed C-DML circuits. The proposed design offers a maximum PDP reduction of 92.66% in static mode and 79.08% in dynamic mode. The effect of temperature and voltage variations on the PDP of both CMOS and proposed CNTFET DML based 2:1 multiplexer is also investigated. It is observed that there is negligible effect of temperature on the performance of proposed C-DML based 2:1 multiplexer. A PDP reduction of 77.89%-83.82% in static mode and 82.07%-87.73% in dynamic mode is observed at different voltages. The proposed technique is capable of reducing PDP at all voltages and temperatures.