Low Delay Based Full Adder/Subtractor by MIG and COG Reversible Logic Gate

Reversible logic gates are implemented over a high scalein the future technologies. Reversible logic is seen as a demandingfield with variegated applications like CMOS designs consumingless power. This paper proposed design of a full Adder/Subtractorcircuitry with the help of fault tolerant based Reversible logic gates. In the given paper, a full adder/subtractor is proposed with help ofMIG (Modified Islam Gate) & COG (Controlled Operation Gate)reversible logic gate comprised of pipelining. As observed from theoutcome session, it is evident that delay will be minimized by around61% by making use of COG & MIG Reversible logic gatescontrasting Feynman Double Gate based Full Adder/Subtractor.