J. R. Rusli, R. Sidek, Hasmayadi Majid, W.Z. Wan Hassand, M. A. Mustafa, S. Shafie
{"title":"低压低功率PVT动态比较器的设计与验证","authors":"J. R. Rusli, R. Sidek, Hasmayadi Majid, W.Z. Wan Hassand, M. A. Mustafa, S. Shafie","doi":"10.1109/ICSIMA.2018.8688785","DOIUrl":null,"url":null,"abstract":"This paper presents a low voltage low power dynamic comparator with 45 process corners verification. In 45 process corner simulation, circuit is simulated with 10% voltage supply variation, five process corners FF, SS, TT, FS, SF variation and temperature variation in between 0°C to 100°C. The comparator is simulated in 0.18µm CMOS technology with supply voltage 0.8 volt using Virtuoso Cadence tool. From simulated result, significant improvement on power consumption and delay is achieved during worst case condition. Details on verification method are presented in this paper.","PeriodicalId":222751,"journal":{"name":"2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation\",\"authors\":\"J. R. Rusli, R. Sidek, Hasmayadi Majid, W.Z. Wan Hassand, M. A. Mustafa, S. Shafie\",\"doi\":\"10.1109/ICSIMA.2018.8688785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low voltage low power dynamic comparator with 45 process corners verification. In 45 process corner simulation, circuit is simulated with 10% voltage supply variation, five process corners FF, SS, TT, FS, SF variation and temperature variation in between 0°C to 100°C. The comparator is simulated in 0.18µm CMOS technology with supply voltage 0.8 volt using Virtuoso Cadence tool. From simulated result, significant improvement on power consumption and delay is achieved during worst case condition. Details on verification method are presented in this paper.\",\"PeriodicalId\":222751,\"journal\":{\"name\":\"2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSIMA.2018.8688785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSIMA.2018.8688785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation
This paper presents a low voltage low power dynamic comparator with 45 process corners verification. In 45 process corner simulation, circuit is simulated with 10% voltage supply variation, five process corners FF, SS, TT, FS, SF variation and temperature variation in between 0°C to 100°C. The comparator is simulated in 0.18µm CMOS technology with supply voltage 0.8 volt using Virtuoso Cadence tool. From simulated result, significant improvement on power consumption and delay is achieved during worst case condition. Details on verification method are presented in this paper.