XBOX系列X:下一代游戏主机SoC

P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad
{"title":"XBOX系列X:下一代游戏主机SoC","authors":"P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad","doi":"10.1109/ISSCC42613.2021.9366057","DOIUrl":null,"url":null,"abstract":"The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 \\times$ GPU performance, $3 \\times$ CPU performance, $2.4 \\times$ GPU performance/W, $1.7 \\times$ memory bandwidth and $2 \\times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $\\mathrm{a}52.5 \\times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"XBOX Series X: A Next-Generation Gaming Console SoC\",\"authors\":\"P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad\",\"doi\":\"10.1109/ISSCC42613.2021.9366057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 \\\\times$ GPU performance, $3 \\\\times$ CPU performance, $2.4 \\\\times$ GPU performance/W, $1.7 \\\\times$ memory bandwidth and $2 \\\\times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $\\\\mathrm{a}52.5 \\\\times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.\",\"PeriodicalId\":371093,\"journal\":{\"name\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42613.2021.9366057\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9366057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

XBOX系列X片上系统(SoC)比上一代有了巨大的改进,GPU性能高达$2 \倍,CPU性能为$3 \倍,GPU性能/W为$2.4 \倍,内存带宽为$1.7 \倍,IO带宽为$2 \倍,可提供图3.1.1所示的额外处理能力和功能。该芯片采用台积电的N7工艺节点[6]制造,在360.4mm2的芯片上包含153亿个晶体管。它采用12层(5-2-5)基板,封装在$\ mathm {a}52.5 \times 52.5$ mm2 BGA中,具有2963个球,最小球间距为0.80mm。模具照片如图3.1.7所示。io限制的芯片平面图是由芯片3面上的DRAM连接驱动的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
XBOX Series X: A Next-Generation Gaming Console SoC
The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 \times$ GPU performance, $3 \times$ CPU performance, $2.4 \times$ GPU performance/W, $1.7 \times$ memory bandwidth and $2 \times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $\mathrm{a}52.5 \times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信