一个完全集成的GPS接收器前端，功耗为40兆瓦

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993099

M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland

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引用次数: 35

摘要

一个0.25 /spl mu/m CMOS正交复杂带通低中频GPS接收机包括一个LNA、锁相环、混频器和一个连续时间/spl Delta//spl Sigma/ ADC。该芯片具有-130 dBm的输入灵敏度，62 dB DR和-32 dB IMRR，同时从2v电源消耗40 mW。芯片是9毫米/sup 2/。

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A fully-integrated GPS receiver front-end with 40 mW power consumption

A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.

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来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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