A multi-region trap characterization method and its reliability application on STI-based high-voltage LDMOSFETs

The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.