{"title":"新型能量回收CMOS XNOR/XOR门","authors":"Y. Xu, A. Srivastava","doi":"10.1109/MWSCAS.2007.4488723","DOIUrl":null,"url":null,"abstract":"In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"New energy recovery CMOS XNOR/XOR gates\",\"authors\":\"Y. Xu, A. Srivastava\",\"doi\":\"10.1109/MWSCAS.2007.4488723\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.\",\"PeriodicalId\":256061,\"journal\":{\"name\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 50th Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2007.4488723\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 50th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2007.4488723","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
本文提出了一种新型能量回收CMOS XNOR/XOR门。这些电路已经使用Cadence/Spectre以及其他三个XNOR/XOR门进行了模拟。结果表明,与时钟绝热逻辑(CAL)相比,新型CMOS XNOR/XOR门功耗降低30%。采用标准的0.5 μ m n阱CMOS工艺制作的新型能量回收CMOS XNOR/XOR门的实验结果与仿真结果一致。
In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.