{"title":"图形IP的硬件/固件验证","authors":"Romain Kamdem","doi":"10.1109/RSP.2007.25","DOIUrl":null,"url":null,"abstract":"This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.","PeriodicalId":262928,"journal":{"name":"IEEE International Workshop on Rapid System Prototyping","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Hardware/Firmware Verification of Graphic IP\",\"authors\":\"Romain Kamdem\",\"doi\":\"10.1109/RSP.2007.25\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.\",\"PeriodicalId\":262928,\"journal\":{\"name\":\"IEEE International Workshop on Rapid System Prototyping\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RSP.2007.25\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RSP.2007.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.
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