{"title":"减小CMOS电流放大器输入阻抗的设计方法","authors":"Simeon Dimitrov Kostadinov","doi":"10.1109/ET.2019.8878647","DOIUrl":null,"url":null,"abstract":"This paper presents a basic current amplifier block, defines its performance parameters and describes some design approaches to optimize them. Several versions of the amplifier are designed and compared using 32nm CMOS technology. The goal of the comparison is to study how different approaches for reducing of the input impedance affects the other amplifier parameters: bandwidth, output impedance, nonlinearity.","PeriodicalId":306452,"journal":{"name":"2019 IEEE XXVIII International Scientific Conference Electronics (ET)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design Approaches for Reducing the Input Impedance of CMOS Current Amplifier\",\"authors\":\"Simeon Dimitrov Kostadinov\",\"doi\":\"10.1109/ET.2019.8878647\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a basic current amplifier block, defines its performance parameters and describes some design approaches to optimize them. Several versions of the amplifier are designed and compared using 32nm CMOS technology. The goal of the comparison is to study how different approaches for reducing of the input impedance affects the other amplifier parameters: bandwidth, output impedance, nonlinearity.\",\"PeriodicalId\":306452,\"journal\":{\"name\":\"2019 IEEE XXVIII International Scientific Conference Electronics (ET)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE XXVIII International Scientific Conference Electronics (ET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ET.2019.8878647\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE XXVIII International Scientific Conference Electronics (ET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ET.2019.8878647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design Approaches for Reducing the Input Impedance of CMOS Current Amplifier
This paper presents a basic current amplifier block, defines its performance parameters and describes some design approaches to optimize them. Several versions of the amplifier are designed and compared using 32nm CMOS technology. The goal of the comparison is to study how different approaches for reducing of the input impedance affects the other amplifier parameters: bandwidth, output impedance, nonlinearity.
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