基于Maya乘法法优化fpga乘数器的架构设计

2016 IEEE Central America and Panama Student Conference (CONESCAPAN) Pub Date : 2016-09-01 DOI:10.1109/CONESCAPAN.2016.8075212

Fabian Venegas Siordia, J. J. Raygoza Panduro, Edwin Christian Becerra Álvarez, S. O. Cisneros, J. R. Domínguez

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引用次数: 0

摘要

玛雅二进制乘法器是一种简化和优化在fpga中实现的乘法的架构。这个架构是基于玛雅人的乘法方法或Tzeltal。该体系结构利用fpga分组乘法器的并行性来生成部分乘积。通过减少要执行的和的数量来加速乘法。这种新方法提供了改进算术计算的特性。

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Architecture design to optimize multipliers in FPGAs based on Maya multiplying method

The Mayan binary multiplier is an architecture to simplify and optimize the multiplication implemented in FPGAs. This architecture is based on the Maya multiplication method or Tzeltal. The architecture takes advantage of the parallelism of FPGAs grouping multipliers for generating the partial products. The multiplication is accelerated by decreasing the number of sums to be performed. This new approach provides properties that improve arithmetic calculations.

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2016 IEEE Central America and Panama Student Conference (CONESCAPAN)

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