Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC

Leakage power reduction and Power Delivery Network (PDN) are amongst the most challenging areas in modern VLSI design. The focus is on reducing leakage power by using more leakage saving techniques and Multiple power pins (commonly known as MPP) standard cell libraries in the SOC. MPP cells can retain data even when logic modules in the design are in the power off state. But extensive usage of MPP cells comes with an overhead of backup supply power grid which eats up the routing resources thereby increasing the routing congestion, physical design and layout convergence challenges in high utilization designs. The backup supply power grid needs to meet the voltage IR drop requirements. So the problem statement is not only restricted to saving leakage, it is more of saving leakage while targeting high frequency and high utilization with a power grid meeting IR drop limits and without causing timing and layout convergence challenges. To solve this problem, optimized and robust backup supply power grid planning along with its verification is proposed in this paper which enables the extensive use of MPP cell addition while achieving high utilization. As an application of the proposed approach, around 20% of leakage power reduction is achieved due to the addition of auto power gating features without increasing layout convergence challenges and the IR drop issues. The proposed technique can be used during the ECO mode as well if some MPP cells are added during ECO phase.