非结构化网格上非连续Galerkin浅水模型的可扩展多fpga设计

Jennifer Faj, Tobias Kenter, S. Faghih-Naini, Christian Plessl, V. Aizinger
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引用次数: 2

摘要

fpga作为科学模拟的节能加速器,包括在非结构化网格上操作的方法,正在培养人们的兴趣。考虑到对高性能计算的潜在影响,需要特别注意这些方法的可伸缩性。在这种情况下,FPGA硬件和软件堆栈的网络功能可以发挥关键作用,使解决方案超越传统的主机- mpi和加速器-卸载模型。在这项工作中,我们使用fpga之间的直接低延迟流通信,提出了不连续伽辽金浅水模型的多fpga缩放。为此,划分了定义仿真空间域的非结构化网格,配置了fpga间网络以匹配相邻分区的拓扑结构,并将halo通信与数据流计算管道重叠。通过这种方法,我们展示了在多达8个fpga上的强大扩展,并行效率>80%,每个时间步长的执行时间低至7.6 μs。同时,通过弱缩放,该方法允许模拟更大的网格,这将超过单个FPGA的本地内存限制,现在支持多达100,000个元素的网格,并达到高达6.5 TFLOPs的聚合性能。最后,分层分区方法允许在某些设计中更好地利用FPGA计算资源,并且通过减轻通信拓扑带来的限制,可以在8个FPGA上进行多达32个分区的模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes
FPGAs are fostering interest as energy-efficient accelerators for scientific simulations, including for methods operating on unstructured meshes. Considering the potential impact on high-performance computing, specific attention needs to be given to the scalability of such approaches. In this context, the networking capabilites of FPGA hardware and software stacks can play a crucial role to enable solutions that go beyond a traditional host-MPI and accelerator-offload model. In this work, we present the multi-FPGA scaling of a discontinuous Galerkin shallow water model using direct low-latency streaming communication between the FPGAs. To this end, the unstructured mesh defining the spatial domain of the simulation is partitioned, the inter-FPGA network is configured to match the topology of neighboring partitions, and halo communication is overlapped with the dataflow computation pipeline. With this approach, we demonstrate strong scaling on up to eight FPGAs with a parallel efficiency of >80% and execution times per time step of as low as 7.6 μs. At the same time, with weak scaling, the approach allows to simulate larger meshes that would exceed the local memory limits of a single FPGA, now supporting meshes up to more than 100,000 elements and reaching an aggregated performance of up to 6.5 TFLOPs. Finally, a hierarchical partitioning approach allows for better utilization of the FPGA compute resources in some designs and, by mitigating limitations posed by the communication topology, enables simulations with up to 32 partitions on 8 FPGAs.
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