{"title":"用于信号和图像处理的数字VLSI神经处理器的设计","authors":"C. Chang, B. Sheu","doi":"10.1109/NNSP.1991.239480","DOIUrl":null,"url":null,"abstract":"An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm*3.75 cm chip by using the 0.5 mu m CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference.<<ETX>>","PeriodicalId":354832,"journal":{"name":"Neural Networks for Signal Processing Proceedings of the 1991 IEEE Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a digital VLSI neuroprocessor for signal and image processing\",\"authors\":\"C. Chang, B. Sheu\",\"doi\":\"10.1109/NNSP.1991.239480\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm*3.75 cm chip by using the 0.5 mu m CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference.<<ETX>>\",\"PeriodicalId\":354832,\"journal\":{\"name\":\"Neural Networks for Signal Processing Proceedings of the 1991 IEEE Workshop\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Neural Networks for Signal Processing Proceedings of the 1991 IEEE Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NNSP.1991.239480\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Neural Networks for Signal Processing Proceedings of the 1991 IEEE Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NNSP.1991.239480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
设计了一种高效的数据/图像处理单元。详细的通信网络,指令集和电路模块创建环连接和网格连接的收缩阵列为检索和学习阶段的神经网络操作。采用TRW公司的0.5 μ m CMOS技术,可在3.75 cm*3.75 cm的芯片上实现800个处理元件。这个数字神经处理器也可以扩展到支持模糊逻辑推理。
Design of a digital VLSI neuroprocessor for signal and image processing
An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm*3.75 cm chip by using the 0.5 mu m CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference.<>