{"title":"一种新型低压四象限电流模式乘法器","authors":"S. Kaedi, E. Farshidi","doi":"10.1109/IRANIANCEE.2012.6292344","DOIUrl":null,"url":null,"abstract":"In this paper a new CMOS current-mode multiplier based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 1.8 V. The major advantages of this multiplier are low voltage, high speed, low power, immunity of body effect, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters in 0.18μm CMOS technology. The simulation results of analog multiplier demonstrate a THD of 1.24% in 1MHz, a -3dB bandwidth of 31.2MHz and power consumption is less than 207 μW.","PeriodicalId":308726,"journal":{"name":"20th Iranian Conference on Electrical Engineering (ICEE2012)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A new low voltage four-quadrant current mode multiplier\",\"authors\":\"S. Kaedi, E. Farshidi\",\"doi\":\"10.1109/IRANIANCEE.2012.6292344\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new CMOS current-mode multiplier based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 1.8 V. The major advantages of this multiplier are low voltage, high speed, low power, immunity of body effect, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters in 0.18μm CMOS technology. The simulation results of analog multiplier demonstrate a THD of 1.24% in 1MHz, a -3dB bandwidth of 31.2MHz and power consumption is less than 207 μW.\",\"PeriodicalId\":308726,\"journal\":{\"name\":\"20th Iranian Conference on Electrical Engineering (ICEE2012)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"20th Iranian Conference on Electrical Engineering (ICEE2012)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRANIANCEE.2012.6292344\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"20th Iranian Conference on Electrical Engineering (ICEE2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRANIANCEE.2012.6292344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new low voltage four-quadrant current mode multiplier
In this paper a new CMOS current-mode multiplier based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 1.8 V. The major advantages of this multiplier are low voltage, high speed, low power, immunity of body effect, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters in 0.18μm CMOS technology. The simulation results of analog multiplier demonstrate a THD of 1.24% in 1MHz, a -3dB bandwidth of 31.2MHz and power consumption is less than 207 μW.
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