An IP Core of AMBA Bus Interface in HDL

The AMBA on-chip bus architecture is a well-known open specification that explains how to connect and manage the functional units that make up a System-On-Chip (SoC). The design and implementation of an AHB Master, RAM, ROM, FIFO and Memory Controller implementation is proposed in this paper. It is primarily divided into two categories: operation initiator (AHB MASTER) and AHB SLAVE. Furthermore, AHB master generate the operation in burst mode, single transfer according to interface requirement and Address generator, generates the address in increment or wrap mode, as well as completing data transfers with an asymmetric asynchronous FIFO with variable data widths for read and write. A bridge between an AHB Master and an AHB slave will be demonstrated using a memory controller, and their outcome in terms of area and speed will be address ed. A finite state machine will be used to design the control framework. Xilinx Virtex 2 XC2VP40 will be used to implement the AHB Master and Slave IP.