{"title":"实时主存数据库的性能","authors":"S. Van Singel, T. Tabe, N. Soparkar, A. Asthana","doi":"10.1109/MTDT.1995.518089","DOIUrl":null,"url":null,"abstract":"Applications that involve real-time databases (in which the access to data must satisfy certain time constraints), are difficult to implement on standard architectural platforms. A major reason concerns the limited memory bandwidth available in standard systems which the precludes high performance necessary in \"data-intensive\" applications. To address this problem, we propose the use of a logic-enhanced memory (hardware memory enhanced with select programmable processing logic) architecture. We describe experimentation with a limited implementation of a real-time database facility for multiprocessors on a logic-enhanced memory system, and our simulations show that such an approach may provide better performance as compared to standard configurations.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"272 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Performance in real-time main-memory databases\",\"authors\":\"S. Van Singel, T. Tabe, N. Soparkar, A. Asthana\",\"doi\":\"10.1109/MTDT.1995.518089\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Applications that involve real-time databases (in which the access to data must satisfy certain time constraints), are difficult to implement on standard architectural platforms. A major reason concerns the limited memory bandwidth available in standard systems which the precludes high performance necessary in \\\"data-intensive\\\" applications. To address this problem, we propose the use of a logic-enhanced memory (hardware memory enhanced with select programmable processing logic) architecture. We describe experimentation with a limited implementation of a real-time database facility for multiprocessors on a logic-enhanced memory system, and our simulations show that such an approach may provide better performance as compared to standard configurations.\",\"PeriodicalId\":318070,\"journal\":{\"name\":\"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing\",\"volume\":\"272 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1995.518089\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1995.518089","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Applications that involve real-time databases (in which the access to data must satisfy certain time constraints), are difficult to implement on standard architectural platforms. A major reason concerns the limited memory bandwidth available in standard systems which the precludes high performance necessary in "data-intensive" applications. To address this problem, we propose the use of a logic-enhanced memory (hardware memory enhanced with select programmable processing logic) architecture. We describe experimentation with a limited implementation of a real-time database facility for multiprocessors on a logic-enhanced memory system, and our simulations show that such an approach may provide better performance as compared to standard configurations.