A high throughput turbo decoder VLSI architecture for 3GPP LTE standard

This paper presents a highly parallel turbo decoding architecture for 3GPP LTE standard. High throughput is achieved by increasing the decoder parallelism and reducing window sizes. A batcher-sorting-based permutation network is presented which is able to support multi-standard applications. The proposed solution supports all codes specified by 3GPP LTE standard. High coding efficiency is achieved at low computational cost by exploiting an effective scheme for the initialization of forward and backward state metrics. The decoder achieves a maximum throughput of 285 Mbps at 200 MHz, occupying an area of 210 mm2 on 90-nm Standard Cell ASIC technology.